DESIGN AND ANALYSIS OF LOW POWER VLSI BASED SRAM CELL USING CMOS, FINFET AND GNRFET TECHNOLOGIES

Abstract

Graphene nanoribbon field-effect transistors (GNRFETs) has the ability to be processed and fabricated on a massive scale, making them a viable device for beyond-CMOS nanoelectronics. The primary focus of this study is the design of an SRAM cell using 10 transistors and taking into account two different threshold values. Research efforts centered on FinFET and GNRFET during circuit design. Despite claims of higher performance, lower power consumption, and identical reliability at comparable operating points to scaled CMOS circuits, simulation studies demonstrate that GNRFET circuits are more susceptible to variations and errors. The device and CAD groups working with graphene have some difficult engineering, modeling, and simulation problems to solve as a consequence of these results. Keywords: CMOS, GNRFET, VLSI, SRAM, HSpice.