A NOVEL APPROACH FOR DESIGN OF HIGH SPEED LOW POWER MULTIPLIER WITH REVERSIBLE LOGIC USING VEDIC MULTIPLICATION

Abstract

Abstract - The development of multipliers with improved properties is the main goal of this research, with a particular emphasis on speed, power consumption, and lower range complexity. The strategy makes use of reversible logic, a notion that is being used more and more in a variety of industries, including quantum circuits, low-power CMOS circuits, optical data processing, and multipliers. Reversible logic and Vedic mathematics are combined in this work. Specifically, well-known logical concepts such as the Dual Key, reversible Full Adder, and reversible Half Adder, and Kogge Stone Adder are used in the suggested multipliers. The multipliers' effectiveness and performance are enhanced by these concepts. The research classifies multiple multipliers according to reversible logic circuits in order to guarantee better performance. The Xilinx VIVADO technique is then used to simulate and synthesize the intended multipliers. . We plan to use Modified Full Adder [MFA] and Synthesis Based Clock Gating to our proposed Circuit after carefully examining the results of these simulations in order to verify and comprehend the effectiveness and performance of the suggested multiplier designs. Keywords: Full Adder, Half adder, Vedic Multiplier, Reversible Logic, Vedic mathematics, MFA, Reversible gates, RCA.