DESIGNING OF AN AREA EFFICIENT 4*4 VEDIC MULTIPLIER BY USING PASS TRANSISTOR LOGIC AND RIPPLE CARRY ADDER

Abstract

Abstract - One essential component of arithmetic and logical units is a multiplier, which means that modern digital systems must have a low-power, compact, and quickly-designed architecture. The Urdhva-tiryagbhyam sutra provides a special multiplication technique, drawing influence from mathematical concepts found in ancient Indian Vedic texts. We provide an innovative 4-bit Vedic multiplier concept that utilizes pass transistor logic to be realized in CMOS 250nm technology. The multiplier's architecture is painstakingly designed to minimize space footprint, lower power consumption, and lower the number of transistors than in traditional logic systems. Results from our study demonstrate notable improvements in the digital circuit's logical and physical performance metrics. The Vedic multiplier is introduced, and we show significant gains in transistor economy, area usage, and power efficiency, meeting the current need for high-performance, energy-efficient arithmetic system. Index Words: Vedic multiplier; Pass transistor logic Urdhva-triyakbhyam.